1. Field of the Invention
The present invention is related to emitter coupled logic (ECL) circuits and more particularly to ECL circuits exhibiting low power dissipation.
2. Description of the Prior Art
Emitter-coupled logic (ECL) is distinguished from other logic families in that the transistors of an ECL circuit do not saturate during switching operations. As a result, the transistors produce lower propagation delays, and ECL circuits are therefore typically much faster than other logic families. However, the power dissipation and noise immunity of ECL circuits-is the worst of all available logic families. Therefore, ECL circuits are typically used only in special high-speed applications, such as in telecommunication circuitry.
FIG. 1 shows a prior art single level ECL switch 100. ECL switch 100 includes transistor Q.sub.11 having a base connected to ECL input terminal 101, and a transistor Q.sub.12 having a base connected to a reference voltage V.sub.REF. The emitters of transistors Q.sub.11 and Q.sub.12 are commonly connected to a node N.sub.11, which in turn is connected to a supply voltage V.sub.EE (typically -4.5 to -5.2 V) through a current source 102. The collectors of transistors Q.sub.11 and Q.sub.12 are connected to ground through resistors R.sub.11 and R.sub.12, respectively. The collector of transistor Q.sub.12 is also connected to the base of transistor Q.sub.13, whose collector is connected to ground and whose emitter is connected to V.sub.EE through resistor R.sub.13. The emitter of transistor Q.sub.13 is also connected to an ECL output terminal 103.
In operation, low input voltages of -1.4 to -1.8 V and high input voltages of -0.8 V are applied to input terminal 101, while V.sub.REF is maintained at -1.1 to -1.3 V. The output signal at output terminal 103 changes in response to the input voltage at input terminal 101. For example, a low input voltage signal applied to input terminal 101 turns off Q.sub.11, thereby turning on Q.sub.12 and causing all of the current drawn by current source 102 to pass through resistor R.sub.12. The resulting voltage drop across resistor R.sub.12 causes the voltage level at the output terminal 103 to lower by an approximately equal amount, thereby providing a low ECL output state.
Conversely, a high input voltage signal applied to input terminal 101 turns on Q.sub.11 and turns off Q.sub.12, thereby causing all current to pass through resistor R.sub.11. Because a zero voltage drop exists across resistor R.sub.12, 0 V (ground) is applied to the base of transistor Q.sub.13, and the resulting voltage level at output terminal 103 is a diode drop below ground, thereby providing a high ECL output state.
It is noted that the voltage swing at the input terminal is between 600 mV (the difference between a low input voltage of -1.4 V and a high input voltage of -0.8 V) and 1 V (the difference between a low input voltage of -1.8 V and a high input voltage of -0.8 V).
FIG. 2 shows a multiple input ECL OR/NOR gate 200. As with the ECL switch 100 (described above), ECL OR/NOR gate 200 is a single level circuit. ECL OR/NOR gate 200 includes transistors Q.sub.211, Q.sub.212 . . . Q.sub.21n having bases connected to input terminals 201(1), 201(2) . . . 201(n), and a transistor Q.sub.22 having a base connected to reference voltage V.sub.REF. The emitters of transistors Q.sub.211 . . . Q.sub.21n and Q.sub.22 are commonly connected to a node N.sub.21, which in turn is to a supply voltage V.sub.EE through a current source 202. The collectors of transistors Q.sub.211 . . . Q.sub.21n and Q.sub.22 are connected to ground through resistors R.sub.21 and R.sub.22, respectively. The collectors of transistors Q.sub.211 . . . Q.sub.21n are also connected to the base of transistor Q.sub.23, whose collector is connected to ground and Whose emitter is connected to V.sub.EE through resistor R.sub.23. The emitter of transistor Q.sub.23 forms a NOR output terminal 203. The collector of transistor Q.sub.22 is connected to the base of transistor Q.sub.24, whose collector is connected to ground and whose emitter is connected to V.sub.EE through resistor R.sub.24. The emitter of transistor Q.sub.24 forms an OR output terminal 204.
In operation, if any of the input terminals 201(1), 201(2) . . . 201(n) are high, its corresponding transistor Q.sub.211 . . . Q.sub.21n is turned on and Q.sub.22 is turned off. This causes all of the current drawn by current source 202 to pass through resistor R.sub.21. The resulting voltage drop across resistor R.sub.21 is applied to the base of transistor Q.sub.23, thereby providing a low ECL output state at the NOR output terminal 203. At the same time, with transistor Q.sub.22 turned off, little or no current passes through resistor R.sub.22. Therefore, a high voltage is present at the base of transistor Q.sub.24, which creates a high ECL output state at the OR output terminal 204.
Conversely, low signals on all of the input terminals 201(1), 201(2) . . . 201(n) turns off corresponding transistors Q.sub.211 . . . Q.sub.21n and turns on transistor Q.sub.22, thereby causing all current to pass through resistor R.sub.22. The resulting voltage drop across resistor R.sub.22 causes a low ECL output state at output terminal 204. At the same time, with transistors Q.sub.211 . . . Q.sub.21n turned off, a high voltage is applied to the base of transistor Q.sub.23, thereby causing a high ECL output state at the NOR output terminal 203.
FIG. 3 shows a prior art multilevel ECL gate 300. Multilevel ECL logic is used to produce logic gates, such as AND and NAND gates, and other logic circuits which cannot be produced using the single level ECL logic described above. Referring to FIG. 3, the ECL gate 300 includes transistor Q.sub.31 having a base connected to first input terminal 301(1) and a transistor Q.sub.32 having a base connected to a reference voltage V.sub.REH. The emitters of transistors Q.sub.31 and Q.sub.32 are commonly connected to a node N.sub.31. The collectors of transistors Q.sub.31 and Q.sub.32 are connected to ground through resistors R.sub.31 and R.sub.32, respectively. The collector of transistor Q.sub.32 is also connected to the base of transistor Q.sub.33, whose collector is connected to ground and whose emitter is connected to V.sub.EE through resistor R.sub.33. The emitter of transistor Q.sub.33 forms an output terminal 303. ECL gate 300 differs from the single level ECL switch 100 in that the common emitter node N.sub.31 and the collector of transistor Q.sub.32 are connected to the collectors of transistors Q.sub.34 and Q.sub.35, respectively, which form a second differential pair having emitters connected to V.sub.EE through current source 302(1). The base of transistor Q.sub.34 is connected to the emitter of a transistor Q.sub.36 and to V.sub.EE through a second current source 302(2). The collector of transistor Q.sub.36 is connected to ground. A second input terminal 301(2) of the ECL gate 300 is connected to the base of transistor Q.sub.36. Finally, the base of transistor Q.sub.35 is connected to a second reference voltage V.sub.REF2.
In operation, high input voltage signals applied to both input terminals 301(1) and 301(2) turns on Q.sub.31 and Q.sub.34, and transistors Q.sub.32 and Q.sub.35 are turned off. This causes all of the current drawn by current source 302(1) to pass through transistor Q.sub.34, Q.sub.31 and resistor R.sub.31. The resulting zero voltage drop across resistor R.sub.32 causes a high ECL output state at output terminal 303.
Conversely, when a low input voltage is applied to one or more of the input terminal 301(1) and 301(2), at least one of transistors Q.sub.31 and Q.sub.34 remains off and at least one of the corresponding transistors Q.sub.32 and Q.sub.35 is turned on, thereby causing current to pass through resistor R.sub.32. This creates a low voltage at the base of transistor Q.sub.33, thereby creating a low ECL output state at terminal 303.
As mentioned above, the negative aspects of ECL circuits include high power dissipation and low noise immunity. In order to reduce power dissipation, it is desirable to reduce the power supply to approximately -3.3 V. However, with respect to the single level ECL circuitry, this power supply reduction requires that the input voltage swing (voltage variation between high and low input signals) must be reduced to about 400 mV or less. To operate at this voltage swing, the reference voltage V.sub.REF must be very accurately maintained to avoid logic errors due to noise or variations in the V.sub.REF signal. That is, if V.sub.REF drifts above the logic high voltage level or below the logic low voltage level, then the ECL circuit will malfunction. Therefore, to employ a -3.3 V voltage source in prior art single level ECL circuits, the ECL circuits must be limited to small die with minimum bus drops. Further, with respect to single-ended-input, multilevel ECL circuitry, bias considerations require an absolute minimum power supply of -4.2 V for a saturation free circuit operation. These restrictions prevent the production of high gate count ECL/BiCMOS arrays exhibiting low power consumption.